When forming a device or a wiring pattern in a semiconductor wafer, a method is adopted in which a coating substance called resist is coated on the semiconductor wafer, a light exposure mask of a pattern shape (reticule) is overlaid on the resist, and the resist is exposed to light by exposing such light as visual rays/ultraviolet rays from above the reticle, thus forming the pattern. The thus obtained pattern will change in its shape contingently upon the intensity of an irradiated electron beam or the aperture and therefore, for formation of a highly accurate pattern, the workmanship of the pattern needs to be inspected.
For inspection of such a pattern as above, a critical dimension scanning electron microscope (CD-SEM) has been used widely. In a pattern inspection based on the CD-SEM, an arbitrary evaluation point on a semiconductor pattern to be inspected is observed with the CD-SEM and a critical dimension of a width and shape data of the pattern as well are captured from an observed image to evaluate the workmanship of the pattern.
Incidentally, in order to evaluate the pattern shape by image-picking up the pattern on the wafer with the CD-SEM, it is necessary to prepare a recipe for designating the position, magnification and image quality of an evaluation point. The recipe has conventionally been prepared on the CD-SEM but a drastic increase in the number of evaluation points concomitant with recent highly dense integration of a semiconductor has recently been enabling automatic preparation of a recipe from CAD data to gain a mainstream method.
Further, in the field of recent up-to-date semiconductors, the process rule reaches a more minute critical dimension than the wavelength of an exposure light source. For this reason, during transfer of a pattern to a wafer, rays of light for nearby patterns interfere with each other through a phenomenon called OPE (Optical Proximity Effect), bringing about a problem that patterns different from those of the rectile are transferred onto the resist. To avoid this phenomenon, OPC (Optical Proximity Correction) of correcting a pattern to be transferred by adding to the mask a micro pattern for correction has been used generally. The effect of correction by the OPC pattern added to the layout pattern is verified principally with a litho-simulator, so that a critical spot at which the shape changes greatly differently during transfer to the wafer can be extracted automatically as a Hot Spot, a recipe can be generated automatically from the extracted Hot Spot and then, a pattern on the actual wafer can be measured to thereby conduct stringent verification of a finished shape.
Furthermore, the up-to-date lithography tends to adopt a so-called aggressive OPC (using a greater number of OPC patterns) as more intensive OPC (intensifying the degree of deformation of a pattern). In order to adopt the aggressive OPC, a flow of data is needed which is different from the data flow in the conventional rule base OPC. Then, outline data called contour data has become expected. With the contour data, not only the conventional Hot Spot measuring point but also the shape can be evaluated, permitting more accurate verification to be conducted (see Patent Literature 1, for instance).